1. Technical Field
The present invention relates generally to boundary scan testing, and more particularly, to boundary scan testing in integrated circuits incorporating pipelined dynamic logic.
2. Description of the Related Art
Functional tests of integrated circuits and printed circuit boards are necessary to assure defect-free products. Using a low pin-count serial interface, the Joint Test Action Group (JTAG) interface provides a mechanism for testing both the internal features of an integrated circuit and the connections between two integrated circuits mounted on a printed circuit board or other substrate. The details of the JTAG interface are defined by IEEE (Institute of Electrical and Electronics Engineers) standard 1149.1xe2x80x94IEEE Standard Test Access Port and Boundary Scan Architecture. Latches within an integrated circuit permit a manufacturing tester to load test values and latch test results by manipulating the signals in the JTAG interface.
The market for integrated circuits requires increasing speed and functional density as requirements for computing power and storage continue to rise. A technology that has been applied in recent years to an increasing number of microprocessor and other integrated circuits, is dynamic logic, sometimes referred to as xe2x80x9cDomino Logic Circuitsxe2x80x9d. Domino logic circuits are very efficient from a device per gate standpoint. But, due to the dynamic nature of the logic (logic signals exist as pulses propagating through a dynamic logic pipeline, rather than clocked through static stages), testing of integrated circuits containing domino logic typically involves only the input and output of the domino logic blocks. Since the logic is dynamic, there is no mechanism for loading values within the domino logic circuits so that the entire logic state of an integrated circuit can be set. In a typical dynamic logic pipeline, level-sensitive scan design (LSSD) latches are inserted between groups of several levels of dynamic gates. These latches provide the ability to store data within the logic for scan testing, but at a penalty of reduced performance and increased circuit area.
In a wave pipeline, rather than relying on latches to store state, the logic state is maintained within the combinatorial logic circuits. The values that would otherwise be stored in latches are maintained on capacitive nodes within the logic circuits. Because there are no explicit static latches within the wave pipeline interior, the interior of the pipeline cannot be observed or controlled for testing purposes. Static latches could be introduced in the middle of a pipeline, but this defeats the advantages of the wave pipeline constructed solely of cascaded dynamic stages. In light of the foregoing, it would be desirable to provide a method and apparatus for testing dynamic logic pipelines that have no internal latches.
The objective of testing dynamic logic pipelines having no internal latches is accomplished by initially loading a value from a scan chain into a latch, determining whether or not the integrated circuit is transitioning from scan mode to functional mode and discharging an evaluation node within the dynamic logic. The evaluation node is discharged in conformity with the loaded value in response to determining that the integrated circuit is transitioning from scan mode to functional mode.
The above as well as additional objectives, features, and advantages of the present invention will become apparent in the following detailed written description.